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cy8c24223a, cy8c24423a automotive psoc ? programmable system-on-chip cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-52469 rev. *h revised april 24, 2013 features automotive electronics council (aec) q100 qualified powerful harvard-architecture processor ? m8c processor speeds up to 24 mhz ? 8 8 multiply, 32-bit accumulate ? low power at high speed ? operating voltage: 3.0 v to 5.25 v ? automotive temperature range: ?40 c to +85 c advanced peripherals (psoc ? blocks) ? six rail-to-rail analog psoc blocks provide: ? up to 14-bit analog-to-digital converters (adcs) ? up to 9-bit digital-to-analog converters (dacs) ? programmable gain amplifiers (pgas) ? programmable filters and comparators ? four digital psoc blocks provide: ? 8- to 32-bit timers, counters , and pulse width modulators (pwms) ? cyclical redundancy check (crc) and pseudo-random se- quence (prs) modules ? full- or half-duplex uart ? spi master or slave ? connectable to all general purpose i/o (gpio) pins ? complex peripherals by combining blocks precision, programmable clocking ? internal 5% 24- and 48-mhz oscillator ? high accuracy 24 mhz with optional 32-khz crystal and phase-locked loop (pll) ? optional external oscillator, up to 24 mhz ? internal low-speed, low-power oscillator for watchdog and sleep functionality flexible on-chip memory ? 4 kb flash program storage, 1000 erase/write cycles ? 256 bytes sram data storage ? in-system serial programming (issp) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash programmable pin configurations ? 25 ma sink, 10 ma source on all gpios ? pull-up, pull-down, high z, strong, or open drain drive modes on all gpios ? up to 12 analog inputs on gpios [1] ? two 30 ma analog outputs on gpios ? configurable interrupt on all gpios additional system resources ? inter-integrated circuit (i 2 c?) slave, master, or multimaster operation up to 400 khz ? watchdog and sleep timers ? user-configurable low-voltage detection (lvd) ? integrated supervisory circuit ? on-chip precision voltage reference complete development tools ? free development software (psoc designer?) ? full featured, in-circuit em ulator (ice) and programmer ? full-speed emulation ? complex breakpoint structure ? 128 kb trace memory logic block diagram note 1. there are eight standard analog inputs on the gpio. the other four analog inputs connect from the gpio directly to specific s witched-capacitor block inputs. see the psoc technical reference manual for more details. digital system sram 256 bytes interrupt controller sleep and watchdog multiple clock sources (includes imo, ilo, pll, and eco) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flash 4 kb digital block array multiply accum. internal voltage ref. digital clocks por and lvd system resets decimator system resources analog system analog ref analog input muxing i 2 c (1 row, 4 blocks) system bus analog block array (2 columns, 6 blocks) port 2 port 1 analog drivers port 0
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 2 of 50 contents psoc functional overview .............................................. 3 psoc core .................................................................. 3 digital system ............................................................. 3 analog system ............................................................ 4 additional system resources ..................................... 5 psoc device characteristics . ..................................... 5 getting started .................................................................. 6 application notes ........................................................ 6 development kits ........................................................ 6 training ....................................................................... 6 cypros consultants .................................................... 6 solutions library .......................................................... 6 technical support ....................................................... 6 development tools .......................................................... 6 psoc designer software subsyst ems .......... .............. 6 designing with psoc designer ....................................... 7 select components ..................................................... 7 configure components .......... .............. .............. ......... 7 organize and connect .............. .............. ........... ......... 7 generate, verify, and debug ....................................... 7 pinouts .............................................................................. 8 20-pin part pinout ...................................................... 8 28-pin part pinout ...................................................... 9 registers ......................................................................... 10 register conventions ................................................ 10 register mapping tables .......................................... 10 electrical specifications ................................................ 13 absolute maximum ratings .... ................................... 14 operating temperature ............................................ 14 dc electrical characteristics ..................................... 15 ac electrical characteristics ..................................... 27 packaging information ................................................... 36 packaging dimensions .............................................. 36 thermal impedances ................................................ 37 capacitance on crystal pins .............. .............. ........ 37 solder reflow specifications ..................................... 37 development tool selection .. .............. .............. ........... 40 software .................................................................... 40 development kits ...................................................... 40 evaluation tools ........................................................ 40 device programmers ............. .................................... 40 accessories (emulation and programming) .............. 41 ordering information ...................................................... 42 ordering code definitions ..... .................................... 42 reference information ................................................... 43 acronyms .................................................................. 43 reference documents ............................................... 43 document conventions ......... .................................... 44 glossary .................................................................... 44 document history page ................................................. 49 sales, solutions, and legal information ...................... 50 worldwide sales and design s upport ......... .............. 50 products .................................................................... 50 psoc solutions ......................................................... 50
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 3 of 50 psoc functional overview the psoc family consists of many programmable system-on-chips with on-chip cont roller devices. these devices are designed to replace multiple traditional microcontroller unit (mcu)-based system components wi th one, low cost single-chip programmable device. psoc devices include configurable blocks of analog and digita l logic, and programmable interconnects. this architecture ma kes it possible for the user to create customized peripheral configurations that match the requirements of each individual application. additionally, a fast central processing unit (cpu), flash program memory, sram data memory, and configurable i/o are included in a range of convenient pinouts and packages. the psoc architecture, as shown in the logic block diagram on page 1, is comprised of four main areas: psoc core, digital system, analog system, and system resources. configurable global buses allow all the device resources to be combined into a complete custom system. each cy8c24x23a psoc device includes four digital blocks and six analog blocks. depending on the psoc package, up to 24 gpios are also included. the gpios provide access to the global digital and analog interconnects. psoc core the psoc core is a powerful engine that supports a rich feature set. the core includes a cpu, me mory, clocks, and configurable gpio. the m8c cpu core is a powerful processor with speeds up to 24 mhz, providing a four-million instructions per second (mips) 8-bit harvard-architecture microprocessor. the cpu uses an interrupt controller with multiple vectors, to simplify programming of real time embedded events. program execution is timed and protected using the included sleep timer and watchdog timer (wdt). memory includes 4 kb of flash for program storage and 256 bytes of sram for data storag e. program flash uses four protection levels on blocks of 64 bytes, allowing customized software ip protection. the psoc device incorporates flex ible internal clock generators, including a 24-mhz internal main oscillator (imo) accurate to 5% over temperature and voltage. a low-power 32-khz internal low-speed oscillator (ilo) is provided for the sleep timer and wdt. if crystal accuracy is desired, the 32.768-khz external crystal oscillator (eco) is available for use as a real time clock (rtc) and can optionally generate a crystal-accurate 24-mhz system clock using a pll. the clocks, together with programmable clock dividers (as a system resource), provide the flexibility to integrate almost any timing requirement into the psoc device. psoc gpios provide connection to the cpu, digital, and analog resources of the device. each pin?s drive mode may be selected from eight options, allowing grea t flexibility in external inter- facing. every pin also has the capability to generate a system interrupt. digital system the digital system is composed of four digital psoc blocks. each block is an 8-bit resource that can be used alone or combined with other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which are called user modules. figure 1. digital system block diagram digital peripheral configurations include: pwms (8- to 32-bit) pwms with dead band (8- to 24-bit) counters (8- to 32-bit) timers (8- to 32-bit) full- or half-duplex 8-bit uart with selectable parity spi master and slave i 2 c master, slave, or multimaster (implemented in a dedicated i 2 c block) cyclical redundancy checker/generator (16-bit) infrared data association (irda) prs generators (8- to 32-bit) the digital blocks can be conne cted to any gpio through a series of global buses that can route any signal to any pin. the buses also allow for signal multiplexing and for performing logic operations. this configurability frees your designs from the constraints of a fixed peripheral controller. digital blocks are provided in rows of four, where the number of blocks varies by psoc device family. this allows the optimum choice of system resources for your application. family resources are shown in ta b l e 1 on page 5. digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 row 0 dbb00 dbb01 dcb02 dcb03 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect port 2 port 1 port 0
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 4 of 50 analog system the analog system is composed of six configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. analog peripherals are very flexible and can be customized to support specific application requirements. some of the common psoc analog functions for this device (most available as user modules) are: adcs (up to two, with 6- to 14-bit resolution, selectable as incremental, delta-sigma, or successive approximation register (sar)) filters (two- and four-pole band pass, low pass, and notch) amplifiers (up to two, with selectable gain up to 48x) instrumentation amplifiers (one with selectable gain up to 93x) comparators (up to two, with 16 selectable thresholds) dacs (up to two, with 6- to 9-bit resolution) multiplying dacs (up to two, with 6- to 9-bit resolution) high current output drivers (two with 30-ma drive) 1.3 v reference (as a system resource) dtmf dialer modulators correlators peak detectors many other topologies possible analog blocks are arranged in a co lumn of three, which includes one continuous time (ct) and two switched capacitor (sc) blocks, as shown in figure 2 . figure 2. analog system block diagram acb01 block array array input configuration aci1[1:0] asd20 aci0[1:0] p0[4] refin agndin reference generators agndin asd11 interface to digital system m8c interface (address bus, data bus, etc.) analog reference p0[6] p0[2] p0[0] p2[6] p2[4] p2[2] p2[0] asd11 asc22 acb00 asc10 p0[7] p0[5] p0[3] p0[1] p2[3] p2[1] refin bandgap refhi reflo agnd
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 5 of 50 additional system resources system resources, some of which have been previously listed, provide additional capability useful for complete systems. additional resources include a multiplier, decimator, low voltage detection, and power-on reset (por). brief statements describing the merits of each system resource follow: digital clock dividers provide three customizable clock frequencies for use in applications. the clocks can be routed to both the digital and analog systems. additional clocks can be generated using di gital psoc blocks as clock dividers. a multiply accumulate (mac) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in both general math as well as digital filters. the decimator provides a custom hardware filter for digital signal processing applications including the creation of delta-sigma adcs. the i 2 c module provides 0 to 400 kh z communication over two wires. slave, master, and multim aster modes are all supported. lvd interrupts can signal the application of falling voltage levels, while the advanced por circuit eliminates the need for a system supervisor. an internal 1.3-v voltage reference provides an absolute reference for the analog system, including adcs and dacs. psoc device characteristics depending on your psoc device characteristics, the digital an d analog systems can have varying numbers of digital and analog blocks. the following table lists the resources available for specific psoc device groups. the device covered by this data shee t is shown in the highlighted row of the table. table 1. psoc device characteristics psoc part number digital i/o digital rows digital blocks analog inputs analog outputs analog columns analog blocks sram size flash size cy8c29x66 [2] up to 64 4 16 up to 12 4 4 12 2 k 32 k cy8c28xxx up to 44 up to 3 up to 12 up to 44 up to 4 up to 6 up to 12 + 4 [3] 1 k 16 k cy8c27x43 up to 44 2 8 up to 12 4 4 12 256 16 k cy8c24x94 [2] up to 56 1 4 up to 48 2 2 6 1 k 16 k cy8c24x23a [2] up to 24 1 4 up to 12 2 2 6 256 4 k cy8c23x33 up to 26 1 4 up to 12 2 2 4 256 8 k cy8c22x45 [2] up to 38 2 8 up to 38 0 4 6 [3] 1 k 16 k cy8c21x45 [2] up to 24 1 4 up to 24 0 4 6 [3] 512 8 k cy8c21x34 [2] up to 28 1 4 up to 28 0 2 4 [3] 512 8 k cy8c21x23 up to 16 1 4 up to 8 0 2 4 [3] 256 4 k cy8c20x34 [2] up to 28 0 0 up to 28 0 0 3 [3,4] 512 8 k cy8c20xx6 up to 36 0 0 up to 36 0 0 3 [3,4] up to 2 k up to 32 k notes 2. automotive qualified devices available in this group. 3. limited analog functionality. 4. two analog blocks and one capsense ? block.
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 6 of 50 getting started for in-depth information, along with detailed programming details, see the psoc ? technical reference manual . for up-to-date ordering, packaging, and electrical specification information, see the latest psoc device datasheets on the web. application notes cypress application notes are an excellent introduction to the wide variety of possi ble psoc designs. development kits psoc development kits are available online from and through a growing number of regional and global distributors, which include arrow, avnet, digi-key, farnell, future electronics, and newark. training free psoc technical training (on demand, webinars, and workshops), which is available online via www.cypress.com , covers a wide variety of topics and skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to the cypros consultants web site. solutions library visit our growing library of solution focused designs . here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. technical support technical support ? including a searchable knowledge base articles and technical forums ? is also available online. if you cannot find an answer to your question, call our technical support hotline at 1-800-541-4736. development tools psoc designer? is the revolutionary integrated design environment (ide) that you can use to customize psoc to meet your specific application require ments. psoc designer software accelerates system design and ti me to market. develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. then, customize your design by leveraging the dynamically generated application programming interface (api) libraries of code. finally, debug and test your designs with the integrated debug environment, incl uding in-circuit emulation and standard software debug features. psoc designer includes: application editor graphical user interface (gui) for device and user module configuration and dynamic reconfiguration extensive user module catalog integrated source-code editor (c and assembly) free c compiler with no size restrictions or time limits built-in debugger in-circuit emulation built-in support for communication interfaces: ? hardware and software i 2 c slaves and masters ? full-speed usb 2.0 ? up to four full-duplex universal asynchronous receiver/transmitters (uarts), spi master and slave, and wireless psoc designer supports the entire library of psoc 1 devices and runs on windows xp, windows vista, and windows 7. psoc designer software subsystems design entry in the chip-level view, choose a ba se device to work with. then select different onboard analog and digital components that use the psoc blocks, which are called user modules. examples of user modules are adcs, dacs, amp lifiers, and filters. configure the user modules for your chosen application and connect them to each other and to the proper pins. then generate your project. this prepopulates your project with apis and libraries that you can use to program your application. the tool also supports easy development of multiple configurations and dynamic reconfiguration. dynamic reconfiguration makes it possible to change configurations at run time. in essence, this allows you to use more than 100 percent of psoc's resources for an application. code generation tools the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. you can develop your design in c, assembly, or a combination of the two. assemblers . the assemblers allow you to merge assembly code seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and are linked with other software modules to get absolute addressing. c language compilers . c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs for the psoc family devices. the optimizing c compilers provide all of the features of c, tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger psoc designer has a debug environment that provides hardware in-circuit emulation, al lowing you to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow you to read and program and read and write data memory, and read and write i/o registers. you can read and write cpu registers, set and clear breakpoints, and provide program run, halt, and step control. the debugger also allows you to create a trac e buffer of registers and memory locations of interest. online help system the online help system displays on line, context-sensitive help. designed for procedural and quick reference, each functional
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 7 of 50 subsystem has its own context-se nsitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer. in-circuit emulator a low-cost, high-functionality in -circuit emulator (ice) is available for development support. this hardware can program single devices. the emulator consists of a base unit that connects to the pc using a usb port. the base unit is universal and operates with all psoc devices. emulation pods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full-speed (24 mhz) operation. designing with psoc designer the development process for the psoc device differs from that of a traditional fixed function mi croprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variet y of user-selectable functions. the psoc development process can be summarized in the following four steps: 1. select user modules 2. configure user modules 3. organize and connect 4. generate, verify, and debug select components psoc designer provides a library of pre-built, pre-tested hardware peripheral components called "user modules." user modules make selecting and implementing peripheral devices, both analog and digital, simple. configure components each of the user modules you select establishes the basic register settings that implement the selected function. they also provide parameters and properties that allow you to tailor their precise configuration to your part icular application. for example, a pwm user module configures one or more digital psoc blocks, one for each 8 bits of resolution. the user module parameters permit you to establish the pulse width and duty cycle. configure the parame ters and properties to corre- spond to your chosen application. enter values directly or by selecting values from drop-down menus. all the user modules are documented in datasheets that may be viewed directly in psoc designer or on the cypress website. these user module datasheets explain the internal operat ion of the user module and provide performance specificatio ns. each datasheet describes the use of each user module parameter, and other information you may need to successfully implement your design. organize and connect you build signal chains at the chip level by interconnecting user modules to each other and the i/o pins. you perform the selection, configuration, and routing so that you have complete control over all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, you perform the "generate configuration files" step. this causes psoc designer to generate source code that automatic ally configures the device to your specification and provides the software for the system. the generated code provides application programming interfaces (apis) with high-level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. a complete code development environment allows you to develop and customize your applications in c, assembly language, or both. the last step in the development process takes place inside psoc designer's debugger (access by clicking the connect icon). psoc designer downloads the hex image to the ice where it runs at full speed. psoc designer debugging capabil- ities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface prov ides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals.
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 8 of 50 pinouts the automotive cy8c24x23a psoc device is available in a variety of packages which are listed and illustrated in the following t ables. every port pin (labeled with a ?p?) is capable of digital i/o. however, v ss , v dd , and xres are not capable of digital i/o. 20-pin part pinout note 5. these are the issp pins, which are not high z when coming out of por. see the psoc technical reference manual for details. table 2. 20-pin part pinout (s hrink small-outline package (ssop)) pin no. type pin name description figure 3. cy8c24223a 20-pin psoc device digital analog 1 i/o i p0[7] analog column mux input 2 i/o i/o p0[5] analog column mux input and column output 3 i/o i/o p0[3] analog column mux input and column output 4 i/o i p0[1] analog column mux input 5 power v ss ground connection 6 i/o p1[7] i 2 c serial clock (scl) 7 i/o p1[5] i 2 c serial data (sda) 8 i/o p1[3] 9 i/o p1[1] crystal input (xtalin), i 2 c serial clock (scl), issp-sclk [5] 10 power v ss ground connection 11 i/o p1[0] crystal output (xtalout), i 2 c serial data (sda), issp-sdata [5] 12 i/o p1[2] 13 i/o p1[4] optional external clock input (extclk) 14 i/o p1[6] 15 input xres active high external reset with internal pull down 16 i/o i p0[0] analog column mux input 17 i/o i p0[2] analog column mux input 18 i/o i p0[4] analog column mux input 19 i/o i p0[6] analog column mux input 20 power v dd supply voltage legend : a = analog, i = input, and o = output. ssop 1 ai, p0[7] aio, p0[5] aio, p0[3] ai, p0[1] i2c scl, p1[7] i2c sda, p1[5] p1[3] i2c scl, xtalin, p1[1] v ss 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v dd p0[6], ai p0[4], ai p0[2], ai p0[0], ai xres p1[6] p1[4], extclk p1[2] p1[0], xtalout, i2c sda v ss
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 9 of 50 28-pin part pinout note 6. these are the issp pins, which are not high z when coming out of por. see the psoc technical reference manual for details. table 3. 28-pin part pinout (ssop) pin no. type pin name description figure 4. cy8c24423a 28-pin psoc device digital analog 1 i/o i p0[7] analog column mux input 2 i/o i/o p0[5] analog column mux input and column output 3 i/o i/o p0[3] analog column mux input and column output 4 i/o i p0[1] analog column mux input 5 i/o p2[7] 6 i/o p2[5] 7 i/o i p2[3] direct switched capacitor block input 8 i/o i p2[1] direct switched capacitor block input 9 power v ss ground connection 10 i/o p1[7] i 2 c serial clock (scl) 11 i/o p1[5] i 2 c serial data (sda) 12 i/o p1[3] 13 i/o p1[1] crystal input (xtalin), i 2 c serial clock (scl), issp-sclk [6] 14 power v ss ground connection 15 i/o p1[0] crystal output (xtalout), i 2 c serial data (sda), issp-sdata [6] 16 i/o p1[2] 17 i/o p1[4] optional external clock input (extclk) 18 i/o p1[6] 19 input xres active high external reset with internal pull down 20 i/o i p2[0] direct switched capacitor block input 21 i/o i p2[2] direct switched capacitor block input 22 i/o p2[4] external analog ground (agnd) 23 i/o p2[6] external voltage reference (vref) 24 i/o i p0[0] analog column mux input 25 i/o i p0[2] analog column mux input 26 i/o i p0[4] analog column mux input 27 i/o i p0[6] analog column mux input 28 power v dd supply voltage legend : a = analog, i = input, and o = output. ssop 1 ai, p0[7] aio, p0[5] aio, p0[3] ai, p0[1] p2[7] p2[5] ai, p2[3] ai, p2[1] v ss i2c scl, p1[7] i2c sda, p1[5] p1[3] i2c scl, xtalin, p1[1] v ss 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v dd p0[6], ai p0[4], ai p0[2], ai p0[0], ai p2[6], external vref p2[4], external agnd p2[2], ai p2[0], ai xres p1[6] p1[4], extclk p1[2] p1[0], xtalout, i2c sda
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 10 of 50 registers register conventions this section lists the register s of the automotive cy8c24x23a psoc device. for detailed register information, refer to the psoc technical reference manual . the register conventions specific to this section are listed in the following table. register mapping tables the psoc device has a total register address space of 512 bytes. the register space is re ferred to as i/o space and is divided into two banks, bank 0 and bank 1. the xio bit in the flag register (cpu_f) determines which bank the user is currently in. when the xio bit is set to ?1?, the user is in bank 1. note in the following register mapping tables, blank fields are reserved and must not be accessed. table 4. abbreviations convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 11 of 50 table 5. register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw 40 asc10cr0 80 rw c0 prt0ie 01 rw 41 asc10cr1 81 rw c1 prt0gs 02 rw 42 asc10cr2 82 rw c2 prt0dm2 03 rw 43 asc10cr3 83 rw c3 prt1dr 04 rw 44 asd11cr0 84 rw c4 prt1ie 05 rw 45 asd11cr1 85 rw c5 prt1gs 06 rw 46 asd11cr2 86 rw c6 prt1dm2 07 rw 47 asd11cr3 87 rw c7 prt2dr 08 rw 48 88 c8 prt2ie 09 rw 49 89 c9 prt2gs 0a rw 4a 8a ca prt2dm2 0b rw 4b 8b cb 0c 4c 8c cc 0d 4d 8d cd 0e 4e 8e ce 0f 4f 8f cf 10 50 asd20cr0 90 rw d0 11 51 asd20cr1 91 rw d1 12 52 asd20cr2 92 rw d2 13 53 asd20cr3 93 rw d3 14 54 asc21cr0 94 rw d4 15 55 asc21cr1 95 rw d5 16 56 asc21cr2 96 rw i2c_cfg d6 rw 17 57 asc21cr3 97 rw i2c_scr d7 # 18 58 98 i2c_dr d8 rw 19 59 99 i2c_mscr d9 # 1a 5a 9a int_clr0 da rw 1b 5b 9b int_clr1 db rw 1c 5c 9c dc 1d 5d 9d int_clr3 dd rw 1e 5e 9e int_msk3 de rw 1f 5f 9f df dbb00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbb00dr1 21 w 61 a1 int_msk1 e1 rw dbb00dr2 22 rw 62 a2 int_vc e2 rc dbb00cr0 23 # arf_cr 63 rw a3 res_wdt e3 w dbb01dr0 24 # cmp_cr0 64 # a4 dec_dh e4 rc dbb01dr1 25 w asy_cr 65 # a5 dec_dl e5 rc dbb01dr2 26 rw cmp_cr1 66 rw a6 dec_cr0 e6 rw dbb01cr0 27 # 67 a7 dec_cr1 e7 rw dcb02dr0 28 # 68 a8 mul_x e8 w dcb02dr1 29 w 69 a9 mul_y e9 w dcb02dr2 2a rw 6a aa mul_dh ea r dcb02cr0 2b # 6b ab mul_dl eb r dcb03dr0 2c # 6c ac acc_dr1 ec rw dcb03dr1 2d w 6d ad acc_dr0 ed rw dcb03dr2 2e rw 6e ae acc_dr3 ee rw dcb03cr0 2f # 6f af acc_dr2 ef rw 30 acb00cr3 70 rw rdi0ri b0 rw f0 31 acb00cr0 71 rw rdi0syn b1 rw f1 32 acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 34 acb01cr3 74 rw rdi0lt1 b4 rw f4 35 acb01cr0 75 rw rdi0ro0 b5 rw f5 36 acb01cr1 76 rw rdi0ro1 b6 rw f6 37 acb01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd fd 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved and must not be accessed. # access is bit specific.
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 12 of 50 table 6. register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw 40 asc10cr0 80 rw c0 prt0dm1 01 rw 41 asc10cr1 81 rw c1 prt0ic0 02 rw 42 asc10cr2 82 rw c2 prt0ic1 03 rw 43 asc10cr3 83 rw c3 prt1dm0 04 rw 44 asd11cr0 84 rw c4 prt1dm1 05 rw 45 asd11cr1 85 rw c5 prt1ic0 06 rw 46 asd11cr2 86 rw c6 prt1ic1 07 rw 47 asd11cr3 87 rw c7 prt2dm0 08 rw 48 88 c8 prt2dm1 09 rw 49 89 c9 prt2ic0 0a rw 4a 8a ca prt2ic1 0b rw 4b 8b cb 0c 4c 8c cc 0d 4d 8d cd 0e 4e 8e ce 0f 4f 8f cf 10 50 asd20cr0 90 rw gdi_o_in d0 rw 11 51 asd20cr1 91 rw gdi_e_in d1 rw 12 52 asd20cr2 92 rw gdi_o_ou d2 rw 13 53 asd20cr3 93 rw gdi_e_ou d3 rw 14 54 asc21cr0 94 rw d4 15 55 asc21cr1 95 rw d5 16 56 asc21cr2 96 rw d6 17 57 asc21cr3 97 rw d7 18 58 98 d8 19 59 99 d9 1a 5a 9a da 1b 5b 9b db 1c 5c 9c dc 1d 5d 9d osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbb00fn 20 rw clk_cr0 60 rw a0 osc_cr0 e0 rw dbb00in 21 rw clk_cr1 61 rw a1 osc_cr1 e1 rw dbb00ou 22 rw abf_cr0 62 rw a2 osc_cr2 e2 rw 23 amd_cr0 63 rw a3 vlt_cr e3 rw dbb01fn 24 rw 64 a4 vlt_cmp e4 r dbb01in 25 rw 65 a5 e5 dbb01ou 26 rw amd_cr1 66 rw a6 e6 27 alt_cr0 67 rw a7 e7 dcb02fn 28 rw 68 a8 imo_tr e8 w dcb02in 29 rw 69 a9 ilo_tr e9 w dcb02ou 2a rw 6a aa bdg_tr ea rw 2b 6b ab eco_tr eb w dcb03fn 2c rw 6c ac ec dcb03in 2d rw 6d ad ed dcb03ou 2e rw 6e ae ee 2f 6f af ef 30 acb00cr3 70 rw rdi0ri b0 rw f0 31 acb00cr0 71 rw rdi0syn b1 rw f1 32 acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 34 acb01cr3 74 rw rdi0lt1 b4 rw f4 35 acb01cr0 75 rw rdi0ro0 b5 rw f5 36 acb01cr1 76 rw rdi0ro1 b6 rw f6 37 acb01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd fd 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved and must not be accessed. # access is bit specific.
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 13 of 50 electrical specifications this section presents the dc and ac electr ical specifications of the automotive cy8c 24x23a psoc devices. for the latest electri cal specifications, visit http://www.cypress.com . specifications are valid for ?40 c ? t a ? 85 c and t j ? 100 c, except where noted. refer to table 21 on page 27 for the electrical specifications of the imo using slow imo (slimo) mode. figure 5. voltage versus cpu frequency figure 6. imo frequency trim options 5.25 4.75 93 khz 24 mhz cpu frequency (nominal setting) v dd voltage (v) 0 12 mhz 3.0 v a l id o p e r a t i n g r e g i o n slimo mode = 0 slimo mode = 0 slimo mode = 1 5.25 4.75 6 mhz 24 mhz imo frequency 0 12 mhz 3.0 3.6 slimo mode = 1 v dd voltage (v)
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 14 of 50 absolute maximum ratings exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested. operating temperature table 7. absolute maximum ratings symbol description min typ max units notes t stg storage temperature ?55 25 +100 c higher storage temperatures reduce data retention time. recommended storage temperature is +25 c 25 c. time spent in storage at a temperature greater than 65 c counts toward the flash dr electrical specification in table 20 on page 26. t baketemp bake temperature ? 125 see package label ? c t baketime bake time see package label ? 72 hours t a ambient temperature with power applied ?40 ? +85 c v dd supply voltage on v dd relative to v ss ?0.5 ? +6.0 v v io dc input voltage v ss ? 0.5 ? v dd + 0.5 v v ioz dc voltage applied to tristate v ss ? 0.5 ? v dd + 0.5 v i mio maximum current into any port pin ?25 ? +50 ma esd electrostatic discharge voltage 2000 ? ? v human body model esd. lu latch up current ? ? 200 ma table 8. operating temperature symbol description min typ max units notes t a ambient temperature ?40 ? +85 c t j junction temperature ?40 ? +100 c the temperature rise from ambient to junction is package specific. see table 33 on page 37. the user must limit the power consumption to comply with this requirement.
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 15 of 50 dc electrical characteristics dc chip-level specifications ta b l e 9 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 9. dc chip-level specifications symbol description min typ max units notes v dd supply voltage 3.0 ? 5.25 v see dc por and lvd specifications, table 19 on page 25. i dd supply current ? 5 8 ma conditions are v dd = 5.0 v, cpu = 3 mhz, 48 mhz disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 93.75 khz, analog power = off. imo = 24 mhz. i dd3 supply current ? 3.3 6.0 ma conditions are v dd = 3.3 v, cpu = 3 mhz, 48 mhz disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 93.75 khz, analog power = off. imo = 24 mhz. i sb sleep (mode) current with por, lvd, sleep timer, and wdt. [7] ? 3 6.5 ? a v dd = 3.3 v, ?40 c ? t a ? 55 c, analog power = off. i sbh sleep (mode) current with por, lvd, sleep timer, and wdt at high temperature. [7] ? 4 25 ? a v dd = 3.3 v, 55 c < t a ? 85 c, analog power = off. i sbxtl sleep (mode) current with por, lvd, sleep timer, wdt, and external crystal. [7] ? 4 7.5 ? a conditions are with properly loaded, 1 ? w max, 32.768 khz crystal. v dd = 3.3 v, ?40 c ? t a ? 55 c, analog power = off. i sbxtlh sleep (mode) current with por, lvd, sleep timer, wdt, and external crystal at high temperature. [7] ? 5 26 ? a conditions are with properly loaded, 1 ? w max, 32.768 khz crystal. v dd = 3.3 v, 55 c < t a ? 85 c, analog power = off. v ref reference voltage (bandgap) 1.28 1.30 1.32 v trimmed for appropriate v dd . note 7. standby current includes all functions (por, lvd, wdt, sleep timer) needed for reliable system operation. this must be compar ed with devices that have similar functions enabled.
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 16 of 50 dc gpio specifications ta b l e 1 0 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 10. dc gpio specifications symbol description min typ max units notes r pu pull-up resistor 4 5.6 8 k ? r pd pull-down resistor 4 5.6 8 k ? also applies to the internal pull-down resistor on the xres pin. v oh high output level v dd ? 1.0 ? ? v i oh = 10 ma, v dd = 4.75 to 5.25 v (maximum 40 ma on even port pins (for example, p0[2], p1[4 ]), maximum 40 ma on odd port pins (for example, p0[3], p1[5])). 80 ma maximum combined i oh budget. v ol low output level ? ? 0.75 v i ol = 25 ma, v dd = 4.75 to 5.25 v (maximum 100 ma on even port pins (for example, p0[2], p1[4]), maximum 100 ma on odd port pins (for example, p0[3], p1[5])). 150 ma ma ximum combined i ol budget. i oh high-level source current 10 ? ? ma v oh ? v dd ? 1.0 v, see the limitations of the total current in the note for v oh . i ol low-level sink current 25 ? ? ma v ol ? 0.75 v, see the limitations of the total current in the note for v ol . v il input low level ? ? 0.8 v v ih input high level 2.1 ? v v h input hysteresis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 ? a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. t a = 25 c c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. t a = 25 c
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 17 of 50 dc operational amplifier specifications the following tables list the guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. the operational amplifier is a component of both the analog ct psoc blocks and the analog sc psoc blocks. the guaranteed specifications are measured in the analog ct psoc block. table 11. 5-v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset volta ge (absolute value) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ?1.6 1.3 1.2 10 8 7.5 mv mv mv ? ? tcv osoa average input offset voltage drift ? 7.0 35.0 ? v/c i eboa input leakage current (port 0 analog pins) ? 20 ? pa gross tested to 1 ? a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. t a = 25 c. v cmoa common mode voltage range common mode voltage range (high power or high opamp bias) 0.0 ? v dd v dd ? 0.5 v v the common-mode input voltage range is measured through an analog output buffer. the specification includes the limitations imposed by the characteristics of the analog output buffer. 0.5 ? g oloa open loop gain power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high 60 60 80 ? ? ? ? ? ? db db db specification is applicable at high power. for all other bias modes (except high power, high opamp bias), minimum is 60 db. v ohighoa high output voltage swing (internal signals) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high v dd ? 0.2 v dd ? 0.2 v dd ? 0.5 ? ? ? ? ? ? v v v v olowoa low output voltage swin g (internal signals) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 0.2 0.2 0.5 v v v i soa supply current (including associated agnd buffer) power = low, opamp bias = high power = low, opamp bias = high power = medium, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 150 300 600 1200 2400 4600 200 400 800 1600 3200 6400 ? a ? a ? a ? a ? a ? a psrr oa supply voltage rejection ratio 64 80 ? db v ss ?? v in ?? (v dd ? 2.25 v) or (v dd ? 1.25 v) ?? v in ? v dd .
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 18 of 50 dc low power comparator specifications ta b l e 1 3 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v at 25 c and are for design guidance only. table 12. 3.3-v dc operatio nal amplifier specifications symbol description min typ max units notes v osoa input offset volta ge (absolute value) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ? ? ? 1.65 1.32 ? 10 8 ? mv mv mv power = high, opamp bias = high is not allowed. tcv osoa average input offset voltage drift ? 7.0 35.0 ? v/c i eboa input leakage current (port 0 analog pins) ? 20 ? pa gross tested to 1 ? a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. t a = 25 c v cmoa common mode voltage range 0.2 ? v dd ? 0.2 v the common-mode input voltage range is measured through an analog output buffer. the specification includes the limitations imposed by the characteristics of the analog output buffer. g oloa open loop gain power = low, opamp bias = low power = medium, opamp bias = low power = high, opamp bias = low 60 60 80 ? ? ? ? ? ? db db db specification is applicable at high power. for all other bias modes (except high power, high opamp bias), minimum is 60 db. v ohighoa high output voltage swing (internal signals) power = low, opamp bias = low power = medium, opamp bias = low power = high, opamp bias = low v dd ? 0.2 v dd ? 0.2 v dd ? 0.2 ? ? ? ? ? ? v v v v olowoa low output voltage swin g (internal signals) power = low, opamp bias = low power = medium, opamp bias = low power = high, opamp bias = low ? ? ? ? ? ? 0.2 0.2 0.2 v v v i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 150 300 600 1200 2400 ? 200 400 800 1600 3200 ? ? a ? a ? a ? a ? a ? a power = high, opamp bias = high is not allowed. psrr oa supply voltage rejection ratio 64 80 ? db v ss ?? vin ?? (v dd ? 2.25) or (v dd ? 1.25 v) ?? vin ? v dd . table 13. dc low power comparator specifications symbol description min typ max units notes v reflpc low power comparator (lpc) reference voltage range 0.2 ? v dd ? 1 v i slpc lpc supply current ? 10 40 ? a v oslpc lpc voltage offset ? 2.5 30 mv
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 19 of 50 dc analog output bu ffer specifications the following tables list the guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 14. 5-v dc analog output buffer specifications symbol description min typ max units notes v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? ? v/c v cmob common mode input voltage range 0.5 ? v dd ? 1.0 v r outob output resistance power = low power = high ? ? 1 1 ? ? ? ? v ohighob high output voltage swing (load = 32 ? to v dd /2) power = low power = high 0.5 v dd + 1.1 0.5 v dd + 1.1 ? ? ? ? v v v olowob low output voltage swing (load = 32 ? to v dd /2) power = low power = high ? ? ? ? 0.5 v dd ? 1.3 0.5 v dd ? 1.3 v v i sob supply current including bias cell (no load) power = low power = high ? ? 1.1 2.6 5.1 8.8 ma ma psrr ob supply voltage rejection ratio 52 64 ? db v out > (v dd ? 1.25). c l load capacitance ? ? 200 pf this specification applies to the external circuit that is being driven by the analog output buffer. table 15. 3.3-v dc analog output buffer specifications symbol description min typ max units notes v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? ? v/c v cmob common mode input voltage range 0.5 ? v dd ? 1.0 v r outob output resistance power = low power = high ? ? 1 1 ? ? ? ? v ohighob high output voltage swing (load = 1 k ? to v dd /2) power = low power = high 0.5 v dd + 1.0 0.5 v dd + 1.0 ? ? ? ? v v v olowob low output voltage swing (load = 1 k ? to v dd /2) power = low power = high ? ? ? ? 0.5 v dd ? 1.0 0.5 v dd ? 1.0 v v i sob supply current including bias cell (no load) power = low power = high ? ? 0.8 2.0 2.0 4.3 ma ma psrr ob supply voltage rejection ratio 52 64 ? db v out > (v dd ? 1.25). c l load capacitance ? ? 200 pf this specification applies to the external circuit that is being driven by the analog output buffer.
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 20 of 50 dc analog reference specifications the following tables list the guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. the guaranteed specificat ions are measured through the analog continuous ti me psoc blocks. the power levels for agnd refer to the power of the analog continuous time psoc block. the power le vels for refhi and reflo refer to the analog reference control register. the limits stated for agnd include the offset error of the agnd buffer local to the analog continuous time psoc block . reference control power is high. note avoid using p2[4] for digital signaling when using an analog resource that depends on the analog reference. some coupling of the digital signal may appear on the agnd. table 16. 5-v dc analog reference specifications reference arf_cr [5:3] reference power settings symbol reference description min typ max units 0b000 refpower = high opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.136 v dd /2 + 1.288 v dd /2 + 1.409 v v agnd agnd v dd /2 v dd /2 ? 0.138 v dd /2 + 0.003 v dd /2 + 0.132 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.417 v dd /2 ? 1.289 v dd /2 ? 1.154 v refpower = high opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.202 v dd /2 + 1.290 v dd /2 + 1.358 v v agnd agnd v dd /2 v dd /2 ? 0.055 v dd /2 + 0.001 v dd /2 + 0.055 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.369 v dd /2 ? 1.295 v dd /2 ? 1.218 v refpower = medium opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.211 v dd /2 + 1.292 v dd /2 + 1.357 v v agnd agnd v dd /2 v dd /2 ? 0.055 v dd /2 v dd /2 + 0.052 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.368 v dd /2 ? 1.298 v dd /2 ? 1.224 v refpower = medium opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.215 v dd /2 + 1.292 v dd /2 + 1.353 v v agnd agnd v dd /2 v dd /2 ? 0.040 v dd /2 ? 0.001 v dd /2 + 0.033 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.368 v dd /2 ? 1.299 v dd /2 ? 1.225 v 0b001 refpower = high opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.076 p2[4] + p2[6] ? 0.021 p2[4] + p2[6] + 0.041 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.025 p2[4] ? p2[6] + 0.011 p2[4] ? p2[6] + 0.085 v refpower = high opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.069 p2[4] + p2[6] ? 0.014 p2[4] + p2[6] + 0.043 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.029 p2[4] ? p2[6] + 0.005 p2[4] ? p2[6] + 0.052 v refpower = medium opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.072 p2[4] + p2[6] ? 0.011 p2[4] + p2[6] + 0.048 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.031 p2[4] ? p2[6] + 0.002 p2[4] ? p2[6] + 0.057 v refpower = medium opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.070 p2[4] + p2[6] ? 0.009 p2[4] + p2[6] + 0.047 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.033 p2[4] ? p2[6] + 0.001 p2[4] ? p2[6] + 0.039 v
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 21 of 50 0b010 refpower = high opamp bias = high v refhi ref high v dd v dd ? 0.121 v dd ? 0.003 v dd v v agnd agnd v dd /2 v dd /2 ? 0.040 v dd /2 v dd /2 + 0.034 v v reflo ref low v ss v ss v ss + 0.006 v ss + 0.019 v refpower = high opamp bias = low v refhi ref high v dd v dd ? 0.083 v dd ? 0.002 v dd v v agnd agnd v dd /2 v dd /2 ? 0.040 v dd /2 ? 0.001 v dd /2 + 0.033 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.016 v refpower = medium opamp bias = high v refhi ref high v dd v dd ? 0.075 v dd ? 0.002 v dd v v agnd agnd v dd /2 v dd /2 ? 0.040 v dd /2 ? 0.001 v dd /2 + 0.032 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.015 v refpower = medium opamp bias = low v refhi ref high v dd v dd ? 0.074 v dd ? 0.002 v dd v v agnd agnd v dd /2 v dd /2 ? 0.040 v dd /2 ? 0.001 v dd /2 + 0.032 v v reflo ref low v ss v ss v ss + 0.002 v ss + 0.014 v 0b011 refpower = high opamp bias = high v refhi ref high 3 bandgap 3.753 3.874 3.979 v v agnd agnd 2 bandgap 2.511 2.590 2.657 v v reflo ref low bandgap 1.243 1.297 1.333 v refpower = high opamp bias = low v refhi ref high 3 bandgap 3.767 3.881 3.974 v v agnd agnd 2 bandgap 2.518 2.592 2.652 v v reflo ref low bandgap 1.241 1.295 1.330 v refpower = medium opamp bias = high v refhi ref high 3 bandgap 2.771 3.885 3.979 v v agnd agnd 2 bandgap 2.521 2.593 2.649 v v reflo ref low bandgap 1.240 1.295 1.331 v refpower = medium opamp bias = low v refhi ref high 3 bandgap 3.771 3.887 3.977 v v agnd agnd 2 bandgap 2.522 2.594 2.648 v v reflo ref low bandgap 1.239 1.295 1.332 v 0b100 refpower = high opamp bias = high v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.481 + p2[6] 2.569 + p2[6] 2.639 + p2[6] v v agnd agnd 2 bandgap 2.511 2.590 2.658 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.515 ? p2[6] 2.602 ? p2[6] 2.654 ? p2[6] v refpower = high opamp bias = low v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.498 + p2[6] 2.579 + p2[6] 2.642 + p2[6] v v agnd agnd 2 bandgap 2.518 2.592 2.652 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.513 ? p2[6] 2.598 ? p2[6] 2.650 ? p2[6] v refpower = medium opamp bias = high v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.504 + p2[6] 2.583 + p2[6] 2.646 + p2[6] v v agnd agnd 2 bandgap 2.521 2.592 2.650 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.513 ? p2[6] 2.596 ? p2[6] 2.649 ? p2[6] v refpower = medium opamp bias = low v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.505 + p2[6] 2.586 + p2[6] 2.648 + p2[6] v v agnd agnd 2 bandgap 2.521 2.594 2.648 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.513 ? p2[6] 2.595 ? p2[6] 2.648 ? p2[6] v table 16. 5-v dc analog reference specifications (continued) reference arf_cr [5:3] reference power settings symbol reference description min typ max units
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 22 of 50 0b101 refpower = high opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.228 p2[4] + 1.284 p2[4] + 1.332 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.358 p2[4] ? 1.293 p2[4] ? 1.226 v refpower = high opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.236 p2[4] + 1.289 p2[4] + 1.332 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.357 p2[4] ? 1.297 p2[4] ? 1.229 v refpower = medium opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.237 p2[4] + 1.291 p2[4] + 1.337 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.356 p2[4] ? 1.299 p2[4] ? 1.232 v refpower = medium opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.237 p2[4] + 1.292 p2[4] + 1.337 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.357 p2[4] ? 1.300 p2[4] ? 1.233 v 0b110 refpower = high opamp bias = high v refhi ref high 2 bandgap 2.512 2.594 2.654 v v agnd agnd bandgap 1.250 1.303 1.346 v v reflo ref low v ss v ss v ss + 0.011 v ss + 0.027 v refpower = high opamp bias = low v refhi ref high 2 bandgap 2.515 2.592 2.654 v v agnd agnd bandgap 1.253 1.301 1.340 v v reflo ref low v ss v ss v ss + 0.006 v ss + 0.02 v refpower = medium opamp bias = high v refhi ref high 2 bandgap 2.518 2.593 2.651 v v agnd agnd bandgap 1.254 1.301 1.338 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.017 v refpower = medium opamp bias = low v refhi ref high 2 bandgap 2.517 2.594 2.650 v v agnd agnd bandgap 1.255 1.300 1.337 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.015 v 0b111 refpower = high opamp bias = high v refhi ref high 3.2 bandgap 4.011 4.143 4.203 v v agnd agnd 1.6 bandgap 2.020 2.075 2.118 v v reflo ref low v ss v ss v ss + 0.011 v ss + 0.026 v refpower = high opamp bias = low v refhi ref high 3.2 bandgap 4.022 4.138 4.203 v v agnd agnd 1.6 bandgap 2.023 2.075 2.114 v v reflo ref low v ss v ss v ss + 0.006 v ss + 0.017 v refpower = medium opamp bias = high v refhi ref high 3.2 bandgap 4.026 4.141 4.207 v v agnd agnd 1.6 bandgap 2.024 2.075 2.114 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.015 v refpower = medium opamp bias = low v refhi ref high 3.2 bandgap 4.030 4.143 4.206 v v agnd agnd 1.6 bandgap 2.024 2.076 2.112 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.013 v table 16. 5-v dc analog reference specifications (continued) reference arf_cr [5:3] reference power settings symbol reference description min typ max units
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 23 of 50 table 17. 3.3-v dc analog reference specifications reference arf_cr [5:3] reference power settings symbol reference description min typ max units 0b000 refpower = high opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.170 v dd /2 + 1.288 v dd /2 + 1.376 v v agnd agnd v dd /2 v dd /2 ? 0.098 v dd /2 + 0.003 v dd /2 + 0.097 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.386 v dd /2 ? 1.287 v dd /2 ? 1.169 v refpower = high opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.210 v dd /2 + 1.290 v dd /2 + 1.355 v v agnd agnd v dd /2 v dd /2 ? 0.055 v dd /2 + 0.001 v dd /2 + 0.054 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.359 v dd /2 ? 1.292 v dd /2 ? 1.214 v refpower = medium opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.198 v dd /2 + 1.292 v dd /2 + 1.368 v v agnd agnd v dd /2 v dd /2 ? 0.041 v dd /2 v dd /2 + 0.04 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.362 v dd /2 ? 1.295 v dd /2 ? 1.220 v refpower = medium opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.202 v dd /2 + 1.292 v dd /2 + 1.364 v v agnd agnd v dd /2 v dd /2 ? 0.033 v dd /2 v dd /2 + 0.030 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.364 v dd /2 ? 1.297 v dd /2 ? 1.222 v 0b001 refpower = high opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.072 p2[4] + p2[6] ? 0.017 p2[4] + p2[6] + 0.041 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.029 p2[4] ? p2[6] + 0.010 p2[4] ? p2[6] + 0.048 v refpower = high opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.066 p2[4] + p2[6] ? 0.010 p2[4] + p2[6] + 0.043 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.024 p2[4] ? p2[6] + 0.004 p2[4] ? p2[6] + 0.034 v refpower = medium opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.073 p2[4] + p2[6] ? 0.007 p2[4] + p2[6] + 0.053 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.028 p2[4] ? p2[6] + 0.002 p2[4] ? p2[6] + 0.033 v refpower = medium opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.073 p2[4] + p2[6] ? 0.006 p2[4] + p2[6] + 0.056 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.030 p2[4] ? p2[6] p2[4] ? p2[6] + 0.032 v 0b010 refpower = high opamp bias = high v refhi ref high v dd v dd ? 0.102 v dd ? 0.003 v dd v v agnd agnd v dd /2 v dd /2 ? 0.040 v dd /2 + 0.001 v dd /2 + 0.039 v v reflo ref low v ss v ss v ss + 0.005 v ss + 0.020 v refpower = high opamp bias = low v refhi ref high v dd v dd ? 0.082 v dd ? 0.002 v dd v v agnd agnd v dd /2 v dd /2 ? 0.031 v dd /2 v dd /2 + 0.028 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.015 v refpower = medium opamp bias = high v refhi ref high v dd v dd ? 0.083 v dd ? 0.002 v dd v v agnd agnd v dd /2 v dd /2 ? 0.032 v dd /2 ? 0.001 v dd /2 + 0.029 v v reflo ref low v ss v ss v ss + 0.002 v ss + 0.014 v refpower = medium opamp bias = low v refhi ref high v dd v dd ? 0.081 v dd ? 0.002 v dd v v agnd agnd v dd /2 v dd /2 ? 0.033 v dd /2 ? 0.001 v dd /2 + 0.029 v v reflo ref low v ss v ss v ss + 0.002 v ss + 0.013 v 0b011 all power settings not allowed at 3.3 v ??? ? ? ??
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 24 of 50 dc analog psoc block specifications ta b l e 1 5 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. 0b100 all power settings not allowed at 3.3 v ??? ? ? ?? 0b101 refpower = high opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.211 p2[4] + 1.285 p2[4] + 1.348 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.354 p2[4] ? 1.290 p2[4] ? 1.197 v refpower = high opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.209 p2[4] + 1.289 p2[4] + 1.353 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.352 p2[4] ? 1.294 p2[4] ? 1.222 v refpower = medium opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.218 p2[4] + 1.291 p2[4] + 1.351 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.351 p2[4] ? 1.296 p2[4] ? 1.224 v refpower = medium opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.215 p2[4] + 1.292 p2[4] + 1.354 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.352 p2[4] ? 1.297 p2[4] ? 1.227 v 0b110 refpower = high opamp bias = high v refhi ref high 2 bandgap 2.460 2.594 2.695 v v agnd agnd bandgap 1.257 1.302 1.335 v v reflo ref low v ss v ss v ss + 0.01 v ss + 0.029 v refpower = high opamp bias = low v refhi ref high 2 bandgap 2.462 2.592 2.692 v v agnd agnd bandgap 1.256 1.301 1.332 v v reflo ref low v ss v ss v ss + 0.005 v ss + 0.017 v refpower = medium opamp bias = high v refhi ref high 2 bandgap 2.473 2.593 2.682 v v agnd agnd bandgap 1.257 1.301 1.330 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.014 v refpower = medium opamp bias = low v refhi ref high 2 bandgap 2.470 2.594 2.685 v v agnd agnd bandgap 1.256 1.300 1.332 v v reflo ref low v ss v ss v ss + 0.002 v ss + 0.012 v 0b111 all power settings not allowed at 3.3 v ??? ? ? ?? table 17. 3.3-v dc analog reference specifications (continued) reference arf_cr [5:3] reference power settings symbol reference description min typ max units table 18. dc analog psoc block specifications symbol description min typ max units notes r ct resistor unit value (continuous time) ? 12.2 ? k ? c sc capacitor unit value (switched capacitor) ? 80 ? ff
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 25 of 50 dc por and lvd specifications ta b l e 1 9 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. note the bits porlev and vm in the following table refer to bits in the vlt_cr register. see the psoc programmable system-on-chip technical reference manual for more information on the vlt_cr register. table 19. dc por and lvd specifications symbol description min typ max units notes v ppor0 v ppor1 v ppor2 v dd value for ppor trip porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? ? ? 2.36 2.82 4.55 2.40 2.95 4.70 v v v v dd must be greater than or equal to 2.5 v during startup, reset from the xres pin, or reset from watchdog. v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 v dd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.40 2.85 2.95 3.06 4.37 4.50 4.62 4.71 2.45 0 2.92 0 3.02 3.13 4.48 4.64 4.73 4.81 2.51 [8] 2.99 [9] 3.09 3.20 4.55 4.75 4.83 4.95 v v v v v v v v notes 8. always greater than 50 mv above v ppor (porlev=00) for falling supply. 9. always greater than 50 mv above v ppor (porlev=01) for falling sup ply .
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 26 of 50 dc programming specifications ta b l e 2 0 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 20. dc programming specifications symbol description min typ max units notes v ddp v dd for programming and erase 4.5 5.0 5.5 v this specification applies to the functional requirements of external programmer tools v ddlv low v dd for verify 3.0 3.1 3.2 v this specification applies to the functional requirements of external programmer tools v ddhv high v dd for verify 5.1 5.2 5.3 v this specification applies to the functional requirements of external programmer tools v ddiwrite supply voltage for flash write operation 3.0 ? 5.25 v this specification applies to this device when it is executing internal flash writes i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.1 ? ? v i ilp input current when applying v ilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull down resistor. i ihp input current when applying v ihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull down resistor. v olv output low voltage during programming or verify ? ? 0.75 v v ohv output high voltage during programming or verify v dd ? 1.0 ? v dd v flash enpb flash endurance (per block) [10, 11] 1,000 ? ? ? erase/write cycles per block flash ent flash endurance (total) [11, 12] 64,000 ? ? ? erase/write cycles flash dr flash data retention 10 ? ? years notes 10. the erase/write cycle limit per block (flash enpb ) is only guaranteed if the device operates within one voltag e range. voltage ranges are 3.0 v to 3.6 v and 4.75 v to 5.25 v. 11. for the full temperature range, the user must employ a temper ature sensor user module (flash temp) or other temperature senso r, and feed the result to the temperature argument before writing. refer to the flash apis application note an2015 for more information. 12. the maximum total number of allowed erase/write cycles is the minimum flash enpb value multiplied by the number of flash blocks in the device.
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 27 of 50 ac electrical characteristics ac chip-level specifications ta b l e 2 1 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 21. ac chip-level specifications symbol description min typ max units notes f imo24 imo frequency for 24 mhz 22.8 [13] 24 25.2 [13] mhz trimmed for 5 v or 3.3 v operation using factory trim values. see figure 6 on page 13. slimo mode = 0. f imo6 imo frequency for 6 mhz 5.5 [13] 6 6.5 [13] mhz trimmed for 5 v or 3.3 v operation using factory trim values. see figure 6 on page 13. slimo mode = 1. f cpu1 cpu frequency (5 v v dd nominal) 0.089 [13] ? 25.2 [13] mhz minimum cpu frequency is 0.022 mhz when slimo mode = 0. f cpu2 cpu frequency (3.3 v v dd nominal) 0.089 [13] ? 12.6 [13] mhz minimum cpu frequency is 0.022 mhz when slimo mode = 0. f blk5 digital psoc block frequency (5 v v dd nominal) 0 ? 50.4 [13,14] mhz refer to ac digital block specifications on page 32. f blk33 digital psoc block frequency (3.3 v v dd nominal) 0 ? 25.2 [13,14] mhz refer to ac digital block specifications on page 32. f 32k1 ilo frequency 15 32 64 khz this specification applies when the ilo has been trimmed. f 32ku ilo untrimmed frequency 5 ? 100 khz after a reset and before the m8c processor starts to execute, the ilo is not trimmed. f 32k2 external crystal oscillator ? 32.76 8 ? khz accuracy is capacitor and crystal dependent. 50% duty cycle. f pll pll frequency ? 23.98 6 ? mhz is a multiple (x732) of crystal frequency. t pllslew pll lock time 0.5 ? 10 ms refer to figure 7 on page 28. t pllslewslow pll lock time for low gain setting 0.5 ? 50 ms refer to figure 8 on page 28. t os external crystal oscillator startup to 1% ? 1700 2620 ms refer to figure 9 on page 28. t osacc external crystal oscillator startup to 100 ppm ? 2800 3800 ms the crystal oscillator frequency is within 100 ppm of its final value by the end of the t osacc period. correct operation assumes a properly loaded 1 w maximum drive level 32.768 khz crystal. 3.0 v ? v dd ? 5.25 v, ?40 ? c ? t a ? 85 ? c. t xrst external reset pulse width 10 ? ? ? s dc24m 24 mhz duty cycle 40 50 60 % dc ilo ilo duty cycle 20 50 80 % step24m 24 mhz trim step size ? 50 ? khz fout48m 48 mhz output frequency 45.6 [13] 48.0 50.4 [13] mhz trimmed. using factory trim values. f max maximum frequency of signal on row input or row output. ? ? 12.6 [13] mhz sr powerup power supply slew rate ? ? 250 v/ms v dd slew rate during power up. t powerup time between end of por state and cpu code execution ? 16 100 ms power up from 0 v. t jit_imo [15] 24 mhz imo cycle-to-cycle jitter (rms) ? 200 700 ps 24 mhz imo long term n cycle-to-cycle jitter (rms) ? 300 900 ps n = 32 24 mhz imo period jitter (rms) ? 100 400 ps t jit_pll [15] pll cycle-to-cycle jitter (rms) ? 200 800 ps pll long term n cycle-to-cycle jitter (rms) ? 300 1200 ps n = 32 pll period jitter (rms) ? 100 700 ps notes 13. accuracy derived from imo with appropriate trim for v dd range. 14. see the individual user module data sheets for information on maximum frequencies for user modules. 15. refer to cypress jitter specifications application note, understanding datasheet jitter specificati ons for cypress timing products ? an5054 for more information.
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 28 of 50 figure 7. pll lock timing diagram figure 8. pll lock for low gain setting timing diagram figure 9. external crystal oscillator startup timing diagram 24 mhz f pll pll enable t pllslew pll gain 0 t 24 mhz f pll pll enable t pllslewlow pll gain 1 t 32 khz f 32k2 32k select t os t
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 29 of 50 ac gpio specifications ta b l e 2 2 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. figure 10. gpio timing diagram table 22. ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12.6 [16] mhz normal strong mode t risef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns v dd = 4.5 to 5.25 v, 10% to 90% t fallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns v dd = 4.5 to 5.25 v, 10% to 90% t rises rise time, slow strong mode, cload = 50 pf 10 27 ? ns v dd = 3 to 5.25 v, 10% to 90% t falls fall time, slow strong mode, cload = 50 pf 10 22 ? ns v dd = 3 to 5.25 v, 10% to 90% note 16. accuracy derived from imo with appropriate trim for v dd range. tfallf tfalls tris ef trises 90% 10% gpio pin output voltage t risef t rises t fallf t falls
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 30 of 50 ac operational amplifier specifications the following tables list the guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. settling times, slew rates, and gain bandwidth are based on the analog ct psoc block. power = high and opamp bias = high is not allowed at 3.3 v. table 23. 5-v ac operational amplifier specifications symbol description min typ max units t roa rising settling time from 80% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 3.9 0.72 0.62 ? s ? s ? s t soa falling settling time from 20% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 5.9 0.92 0.72 ? s ? s ? s sr roa rising slew rate (20% to 80%) (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.15 1.7 6.5 ? ? ? ? ? ? v/ ? s v/ ? s v/ ? s sr foa falling slew rate (80% to 20%) (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.01 0.5 4.0 ? ? ? ? ? ? v/ ? s v/ ? s v/ ? s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.75 3.1 5.4 ? ? ? ? ? ? mhz mhz mhz e noa noise at 1 khz (power = medium, opamp bias = high) ? 100 ? nv/rt-hz table 24. 3.3-v ac operatio nal amplifier specifications symbol description min typ max units t roa rising settling time from 80% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 3.92 0.72 ? s ? s t soa falling settling time from 20% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 5.41 0.72 ? s ? s sr roa rising slew rate (20% to 80%) (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.31 2.7 ? ? ? ? v/ ? s v/ ? s sr foa falling slew rate (80% to 20%) (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.24 1.8 ? ? ? ? v/ ? s v/ ? s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high 0.67 2.8 ? ? ? ? mhz mhz e noa noise at 1 khz (power = medium, opamp bias = high) ? 100 ? nv/rt-hz
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 31 of 50 when bypassed by a capacitor on p2[4], the noise of the analog ground signal distributed to each bl ock is reduced by a factor o f up to 5 (14 db). this is at frequencies above the corner frequency defined by the on-chip 8.1 k ? resistance and the external capacitor. figure 11. typical agnd noise with p2[4] bypass at low frequencies, the opamp noise is proportional to 1/ f, power independent, and determined by device geometry. at high frequencies, increased power level reduces the noise spectrum level. figure 12. typical opamp noise ? 100 1000 10000 0.001 0.01 0.1 1 10 100 fr eq ( khz) nv/rthz 0 0.01 0.1 1.0 10 10 100 1000 10000 0.001 0.01 0.1 1 10 100 freq (khz) nv/rthz ph_ bh ph_ bl pm_bl pl_ bl
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 32 of 50 ac low power comparator specifications ta b l e 2 5 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. ac digital block specifications ta b l e 2 6 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 25. ac low power comparator specifications symbol description min typ max units notes t rlpc lpc response time ? ? 50 ? s ? 50 mv overdrive comparator reference set within v reflpc table 26. ac digital block specifications function description min typ max units notes all functions block input clock frequency v dd ? 4.75 v ? ? 50.4 [18] mhz v dd < 4.75 v ? ? 25.2 [18] mhz timer input clock frequency no capture, v dd ? 4.75 v ? ? 50.4 [18] mhz no capture, v dd < 4.75 v ? ? 25.2 [18] mhz with capture ? ? 25.2 [18] mhz capture pulse width 50 [17] ??ns counter input clock frequency no enable input, v dd ? 4.75 v ? ? 50.4 [18] mhz no enable input, v dd < 4.75 v ? ? 25.2 [18] mhz with enable input ? ? 25.2 [18] mhz enable input pulse width 50 [17] ??ns dead band kill pulse width asynchronous restart mode 20 ? ? ns synchronous restart mode 50 [17] ??ns disable mode 50 [17] ??ns input clock frequency v dd ? 4.75 v ? ? 50.4 [18] mhz v dd < 4.75 v ? ? 25.2 [18] mhz crcprs (prs mode) input clock frequency v dd ? 4.75 v ? ? 50.4 [18] mhz v dd < 4.75 v ? ? 25.2 [18] mhz crcprs (crc mode) input clock frequency ? ? 25.2 [18] mhz spim input clock frequency ? ? 8.4 [18] mhz the spi serial clock (sclk) frequency is equal to the input clock frequency divided by 2. spis input clock (sclk) frequency ? ? 4.2 [18] mhz the input clock is the spi sclk in spis mode. width of ss_negated between transmissions 50 [17] ??ns transmitter input clock frequency the baud rate is equal to the input clock frequency divided by 8. v dd ? 4.75 v, 2 stop bits ? ? 50.4 [18] mhz v dd ? 4.75 v, 1 stop bit ? ? 25.2 [18] mhz v dd < 4.75 v ? ? 25.2 [18] mhz receiver input clock frequency the baud rate is equal to the input clock frequency divided by 8. v dd ? 4.75 v, 2 stop bits ? ? 50.4 [18] mhz v dd ? 4.75 v, 1 stop bit ? ? 25.2 [18] mhz v dd < 4.75 v ? ? 25.2 [18] mhz notes 17. 50 ns minimum input pulse width is based on the input synchronizers running at 24 mhz (42 ns nominal period). 18. accuracy derived from imo with appropriate trim for v dd range.
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 33 of 50 ac analog output buffer specifications the following tables list the guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 27. 5-v ac analog output buffer specifications symbol description min typ max units t rob rising settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 2.5 2.5 ? s ? s t sob falling settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 2.2 2.2 ? s ? s sr rob rising slew rate (20% to 80%), 1 v step, 100 pf load power = low power = high 0.65 0.65 ? ? ? ? v/ ? s v/ ? s sr fob falling slew rate (80% to 20%), 1 v step, 100 pf load power = low power = high 0.65 0.65 ? ? ? ? v/ ? s v/ ? s bw ob small signal bandwidth, 20 mv pp , 3db bw, 100 pf load power = low power = high 0.8 0.8 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1 v pp , 3db bw, 100 pf load power = low power = high 300 300 ? ? ? ? khz khz table 28. 3.3-v ac analog output buffer specifications symbol description min typ max units t rob rising settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 3.8 3.8 ? s ? s t sob falling settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 2.6 2.6 ? s ? s sr rob rising slew rate (20% to 80%), 1 v step, 100 pf load power = low power = high 0.5 0.5 ? ? ? ? v/ ? s v/ ? s sr fob falling slew rate (80% to 20%), 1 v step, 100 pf load power = low power = high 0.5 0.5 ? ? ? ? v/ ? s v/ ? s bw ob small signal bandwidth, 20 mv pp , 3db bw, 100 pf load power = low power = high 0.7 0.7 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1 v pp , 3db bw, 100 pf load power = low power = high 200 200 ? ? ? ? khz khz
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 34 of 50 ac external clock specifications the following tables list the guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. ac programming specifications ta b l e 3 1 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 29. 5 v ac external clock specifications symbol description min typ max units f oscext frequency 0.093 ?24.6mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ?ns ? power-up imo to switch 150 ? ? ? s notes 19. maximum cpu frequency is 12 mhz nominal at 3.3 v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequen cy and duty cycle requirements. 20. if the frequency of the external clock is greater than 12 mhz, the cpu clock divider must be set to 2 or greater. in this ca se, the cpu clock divider ensures that the fifty percent duty cycle requirement is met. 21. for the full temperature range, the user must employ a temperature sensor user module (flashtemp) or other temperature senso r, and feed the result to the temperature argument before writing. refer to the flash apis application note an2015 for more information. table 30. 3.3 v ac external clock specifications symbol description min typ max units f oscext frequency with cpu clock divide by 1 [19] 0.093 ?12.3mhz f oscext frequency with cpu clock divide by 2 or greater [20] 0.186 ?24.6mhz ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ?ns ? power-up imo to switch 150 ? ? ? s table 31. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data setup time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time per block ? 20 80 [21] ms t write flash block write time ? 80 320 [21] ms t dsclk data out delay from falling edge of sclk ? ? 45 ns v dd ? 3.6 t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 ? v dd ? 3.6 t eraseall flash erase time (bulk) ? 20 ? ms erase all blocks and protection fields at once t prgh total flash block program time (t eraseb + t write ), hot ? ? 200 [21] ms t j ? 0c t prgc total flash block program time (t eraseb + t write ), cold ? ? 400 [21] ms t j ? 0c
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 35 of 50 ac i 2 c specifications ta b l e 3 2 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. figure 13. definition for timing for fast/standard mode on the i 2 c bus table 32. ac characteristics of the i 2 c sda and scl pins symbol description standard mode fast mode units min max min max f scli2c scl clock frequency 0 100 [22] 0400 [22] khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? ? s t highi2c high period of the scl clock 4.0 ?0.6 ? ? s t sustai2c setup time for a repeated start condition 4.7 ?0.6 ? ? s t hddati2c data hold time 0 ?0 ? ? s t sudati2c data setup time 250 ?100 [23] ?ns t sustoi2c setup time for stop condition 4.0 ?0.6 ? ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ? 0 50 ns notes 22. f scli2c is derived from sysclk of the psoc. this specification assumes that sysclk is oper ating at 24 mhz, nominal. if sysclk is at a lower frequency, then the f scli2c specification adjusts accordingly. 23. a fast-mode i2c-bus device can be used in a standard-mode i2c-bus system, but the requirement t sudati2c ? 250 ns must then be met. th is is automatically the case if the device does not stretch the low period of the scl signal. if such device does stretc h the low period of the scl sig nal, it must output the next data bit to the sda line t rmax + t sudati2c = 1000 + 250 = 1250 ns (according to the standard-mode i2c-bus specification) before the scl line is released. i2c_sda i2c_scl s sr s p t bufi2c t spi2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c start condition repeated start condition stop condition
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 36 of 50 packaging information this section illustrates the packaging spec ifications for the automotiv e cy8c24x23a psoc device, along with the thermal impedan ces for the package and the typical package capacitance on crystal pins. important note emulation tools may require a larger area on the target pcb than the chip?s footprint. for a det ailed description of the emulation tools? dimensions, refe r to the emulator pod drawings at http://www.cypress.com . packaging dimensions figure 14. 20-pin (210-mil) ssop 51-85077 *e
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 37 of 50 figure 15. 28-pin (210-mil) ssop thermal impedances capacitance on crystal pins solder reflow specifications ta b l e 3 5 shows the solder reflow temperature limits that must not be exceeded. 51-85079 *e table 33. thermal impedances per package package typical ? ja [24] 20-pin ssop 117 c/w 28-pin ssop 101 c/w table 34. capacitance on crystal pins package package capacitance 20-pin ssop 2.6 pf 28-pin ssop 2.8 pf table 35. solder reflow specifications package maximum peak temperature (t c ) maximum time above t c ? 5 c 20-pin ssop 260 ? c 30 seconds 28-pin ssop 260 ? c 30 seconds note 24. t j = t a + power ? ja
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 38 of 50 figure 16. 20-pin ssop carrier tape drawing 51-51101 *c
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 39 of 50 figure 17. 28-pin ssop carrier tape drawing 51-51100 *c table 36. tape and reel specifications package cover tape width (mm) hub size (inches) minimum leading empty pockets minimum trailing empty pockets standard full reel quantity 20-pin ssop 13.3 4 42 25 2000 28-pin ssop 13.3 7 42 25 1000
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 40 of 50 development tool selection this section presents the development tools available for the cy8c24x23a family. software psoc designer ? at the core of the psoc development software suite is psoc designer, used to generate psoc firmware applications. psoc designer is available free of charge at http://www.cypress.com and includes a free c compiler. psoc programmer flexible enough to be used on the bench in development, yet suitable for factory programming, psoc programmer works either as a standalone programming application or it can operate directly from psoc designer or psoc express. psoc programmer software is compatible with both psoc ice-cube in-circuit emulator and psoc miniprog. psoc programmer is available free of charge at http://www.cypress.com. development kits all development kits can be purc hased from the cypress online store. the online store also has the most up to date information on kit contents, descriptions, and availability. cy3215-dk basic development kit the cy3215-dk is for prototyping and development with psoc designer. this kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the contents of specif ic memory locations. advanced emulation features are also su pported through psoc designer. the kit includes: ice-cube unit 28-pin pdip emulation pod for cy8c29466-24pxi 28-pin cy8c29466-24pxi pdip psoc device samples (two) psoc designer software cd issp cable minieval socket programming and evaluation board backward compatibility cable (for connecting to legacy pods) universal 110/220 power supply (12 v) european plug adapter usb 2.0 cable getting started guide development kit registration form evaluation tools all evaluation tools can be purchased from the cypress online store . cy3210-psoceval1 the cy3210-psoceval1 kit features an evaluation board and the miniprog1 programming unit. the evaluation board includes an lcd module, potentiometer, leds, an rs-232 port, and plenty of breadboarding space to meet all of your evaluation needs. the kit includes: evaluation board with lcd module miniprog programming unit 28-pin cy8c29466-24pxi pdip psoc device sample (2) psoc designer software cd getting started guide usb 2.0 cable cy3210-24x23 evaluation pod (evalpod) psoc evalpods are pods that connect to the ice ( cy3215-dk kit) to allow debugging capability. they can also function as a standalone device without debugging capability. the evalpod has a 28-pin dip footprint on the bottom for easy connection to development kits or other hardwar e. the top of the evalpod has prototyping headers for easy connection to the device's pins. cy3210-24x23 provides evaluation of the cy8c24x23a psoc device family. device programmers all device programmers can be purchased from the cypress online store . cy3210-miniprog1 the cy3210-miniprog1 kit allows a user to program psoc devices via the miniprog1 programming unit. the miniprog is a small, compact prototyping programmer that connects to the pc via a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin cy8c29466-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable cy3207issp in-system serial programmer (issp) the cy3207issp is a production programmer. it includes protection circuitry and an industria l case that is more robust than the miniprog in a production-programming environment.
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 41 of 50 note cy3207issp needs special soft ware and is not compatible with psoc programmer. this software is free and can be downloaded from http://www.cypress.com . the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240-v power supply, euro-plug adapter usb 2.0 cable accessories (emula tion and programming) table 37. emulation and programming accessories part number pin package pod kit [25] foot kit [26] adapter [27] CY8C24223A-24PVXA 20-pin ssop cy3250-24x 23a cy3250-20ssop-fk as-20-20-01ss-6 cy8c24423a-24pvxa 28-pin ssop cy3250-24x23a cy 3250-28ssop-fk as-28-28-02ss-6enp-gang notes 25. pod kit contains an emulation pod, a flex-cable (co nnects the pod to the ice), two feet, and device samples. 26. foot kit includes surface mount feet that can be soldered to the target pcb. 27. programming adapter converts non-dip package to dip footprin t. specific details and ordering information for each of the ada pters can be found at http://www.emulation.com .
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 42 of 50 ordering information the following table lists the automotive cy8c24x23a psoc de vice group?s key package features and ordering codes. ordering code definitions table 38. cy8c24x23a automotive psoc device key features and ordering information package ordering code flash (bytes) sram (bytes) temperature range digital blocks analog blocks digital i/o pins analog inputs analog outputs xres pin 20-pin (210-mil) ssop CY8C24223A-24PVXA 4 k 256 ?40 c to +85 c 4 6 16 8 2 yes 20-pin (210-mil) ssop (tape and reel) CY8C24223A-24PVXAt 4 k 256 ?40 c to +85 c 4 6 16 8 2 yes 28-pin (210-mil) ssop cy8c24423a-24pvxa 4 k 256 ?40 c to +85 c 4 6 24 12 [1] 2 yes 28-pin (210-mil) ssop (tape and reel) cy8c24423a-24pvxat 4 k 256 ?40 c to +85 c 4 6 24 12 [1] 2 yes cy 8 c 24 xxx-spxx package type: thermal rating: px = pdip pb-free c = commercial sx = soic pb-free i = industrial pvx = ssop pb-free e = automotive extended ? 40 c to +125 c lfx/lkx = qfn pb-free a = automotive ? 40 c to +85 c ax = tqfp pb-free cpu speed: 24 mhz part number family code technology code: c = cmos marketing code: 8 = psoc company id: cy = cypress
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 43 of 50 reference information acronyms the following table lists the acronyms that are used in this document. reference documents cy8cplc20, cy8cled16p01, cy8c29x66, cy8c27x43, cy8c24 x94, cy8c24x23, cy8c24x23a, cy8c22x13, cy8c21x34, cy8c21x23, cy7c64215, cy7c603xx, cy8cnp1xx, and cywusb6953 psoc ? programmable system-on-chip technical reference manual (trm) (001-14463) design aids ? reading and writing psoc ? flash ? an2015 (001-40459) understanding data sheet jitter specifications for cypress timing products ? an5054 (001-14503) table 39. acronyms used in this datasheet acronym description acronym description ac alternating current mac multiply-accumulate adc analog-to-digital converter mcu microcontroller unit aec automotive electronics council m ips million instructions per second api application programming interface pcb printed circuit board cmos complementary metal oxide semiconductor pdip plastic dual inline package cpu central processing unit pga programmable gain amplifier crc cyclic redundancy check pll phase-locked loop dac digital-to-analog converter por power-on reset dc direct current ppor precision por dtmf dual-tone multi-frequency prs pseudo-random sequence eco external crystal oscillator psoc ? programmable system-on-chip eeprom electrically erasabl e programmable read-only memory pwm pulse-width modulator gpio general-purpose i/o rms root mean square i 2 c inter-integrated circuit rtc real time clock i/o input/output sar successive approximation register ice in-circuit emulator sc switched capacitor ide integrated development environment slimo slow imo ilo internal low speed oscillator spi serial peripheral interface imo internal main oscillator sram static random-access memory irda infrared data association s rom supervisory read-only memory issp in-system serial programming ssop shrunk small outline package lcd liquid crystal display uart universal asynchronous receiver transmitter led light-emitting diode usb universal serial bus lpc low power comparator wdt watchdog timer lvd low-voltage detect xres external reset
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 44 of 50 document conventions units of measure the following table lists the units of me asure that are used in this document. numeric conventions hexadecimal numbers are represented with all letters in uppercase wi th an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? pref ix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, ?01010100b? or ?0 1000011b?). numbers not indicated by an ?h ?, ?b?, or ?0x? are in decimal format. table 40. units of measure symbol unit of measure symbol unit of measure kb 1024 bytes ms millisecond db decibel mv millivolt ? c degree celsius mvpp millivolts peak-to-peak ff femto farad na nanoampere hz hertz ns nanosecond khz kilohertz nv nanovolt k ? kilohm ? ohm mhz megahertz ppm parts per million a microampere % percent s microsecond pa picoampere v microvolt pf picofarad w microwatt ps picosecond ma milliampere v volt mm millimeter w watt glossary active high 1. a logic signal having its asserted state as the logic 1 state. 2. a logic signal having the logic 1 state as the higher voltage of the two states. analog blocks the basic programmable opam p circuits. these are sc (switched capa citor) and ct (continuous time) blocks. these blocks can be interconn ected to provide adcs, dacs , multi-pole filt ers, gain stages, and much more. analog-to-digital converter (adc) a device that changes an analog signal to a digital signal of corresponding magnitude. typically, an adc converts a voltage to a digital number. the digital-to-analog converter (dac) performs the reverse operation. application programming interface (api) a series of software routines that comprise an interfac e between a computer applicat ion and lower level services and functions (for example, user modules and libraries). apis serve as building blocks for prog rammers that create software applications. asynchronous a signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. bandgap reference a stable voltage reference design that matches the posit ive temperature coefficient of vt with the negative temperature coefficient of vbe, to produce a zero temperature coefficient (ideally) reference. bandwidth 1. the frequency range of a message or information processing system measured in hertz. 2. the width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specific ally as, for example, full width at half maximum.
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 45 of 50 bias 1. a systematic deviation of a value from a reference value. 2. the amount by which the average of a set of values departs from a reference value. 3. the electrical, mechanical, magnetic, or other force (field ) applied to a device to establish a reference level to operate the device. block 1. a functional unit that performs a single function, such as an oscillator. 2. a functional unit that may be configured to perform one of several functions, such as a digital psoc block or an analog psoc block. buffer 1. a storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. usually refers to an area reserved for i/o operations, into which da ta is read, or from which data is written. 2. a portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. an amplifier used to lower the output impedance of a system. bus 1. a named connection of nets. bundling nets together in a bus makes it easier to r oute nets with similar routing patterns. 2. a set of signals performing a common function and carry ing similar data. typically represented using vector notation; for example, address[7:0]. 3. one or more conductors that serve as a co mmon connection for a group of related devices. clock the device that generates a period ic signal with a fixed frequency and duty cycle. a clock is sometimes used to synchronize different logic blocks. comparator an electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler a program that translates a high leve l language, such as c, into machine language. configuration space in psoc devices, the register space accessed when the xio bit, in the cpu_f register, is set to ?1?. crystal oscillator an oscillator in whic h the frequency is controlled by a piezoelectric crystal. typically a piezoelectric crystal is less sensitive to ambient te mperature than other circuit components. cyclic redundancy check (crc) a calculation used to detect errors in data communic ations, typically performed using a linear feedback shift register. similar calculations may be used for a va riety of other purposes such as data compression. data bus a bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. more generally, a set of signals used to convey data between digital functions. debugger a hardware and software system that allows you to analyze the operation of the system under development. a debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. dead band a period of time when neither of two or more signals are in their active state or in transition. digital blocks the 8-bit logic bl ocks that can act as a counter, timer, serial receiver, serial transm itter, crc generator, pseudo-random number generator, or spi. digital-to-analog converter (dac) a device that changes a digital signal to an analog signal of corresponding magnitude. the analog-to-digital converter (adc) performs the reverse operation. glossary (continued)
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 46 of 50 duty cycle the relations hip of a clock period high time to its low time, expressed as a percent. emulator duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. external reset (xres) an active high signal that is driven into the psoc devi ce. it causes all operation of the cpu and blocks to stop and return to a pre-defined state. flash an electrically programmable an d erasable, non-volatile technology that provides you the programmability and data storage of eproms, plus in-system erasability. non-volatile means that the data is retained when power is off. flash block the smallest amount of flash rom space that may be programmed at one time and the smallest amount of flash space that may be protected. frequency the number of cycles or events pe r unit of time, for a periodic function. gain the ratio of output current, voltage, or power to input current, voltage, or power, respectively. gain is usually expressed in db. i 2 c a two-wire serial computer bus by philips semiconducto rs (now nxp semiconductors). it is used to connect low-speed peripherals in an embedded system. the original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building contro l electronics. i2c uses only two bi-directional pins, clock and data, both running at the v dd supply voltage and pulled high with resistors. the bus operates up to100 kbits/second in stan dard mode and 400 kbits/second in fast mode. ice the in-circuit emulator that allows you to test the project in a hardware environm ent, while viewing the debugging device activity in a software environment (psoc designer). input/output (i/o) a device that introduces da ta into or extracts data from a system. interrupt a suspension of a process, such as the execution of a computer progra m, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (isr) a block of code that normal code exec ution is diverted to when the cpu receives a hardware interrupt. many interrupt sources may each exist with its own priority and individual isr code block. each isr code block ends with the reti instruction, returning t he device to the point in the program w here it left normal program execution. jitter 1. a misplacement of the timing of a transition from its ideal position. a ty pical form of corruption that occurs on serial data streams. 2. the abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequen cy or phase of successive cycles. low voltage detect (lvd) a circuit that senses v dd and provides an interrupt to the system when v dd falls below a sele cted threshold. m8c an 8-bit harvard-architecture microprocessor. the mi croprocessor coordinates all activity inside a psoc by interfacing to the flash, sram, and register space. master device a device that controls the timing for data exch anges between two devices. or when devices are cascaded in width, the master device is the one that controls th e timing for data exchanges between the cascaded devices and an external interface. the controlled device is called the slave device . glossary (continued)
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 47 of 50 microcontroller an integrated circuit chip that is designed pr imarily for control systems and products. in addition to a cpu, a microcontroller typically incl udes memory, timing circuits, and i/o circuitry. the reason for this is to permit the realization of a controller with a minima l quantity of chips, thus achieving ma ximal possible miniaturization. this in turn, reduces the volume and the cost of the cont roller. the microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal the reference to a circuit containing both analog and digital techniques and components. modulator a device that imposes a signal on a carrier. noise 1. a disturbance that affects a signal and that may distort the information carried by the signal. 2. the random variations of one or mo re characteristics of any entity such as voltage, current, or data. oscillator a circuit that may be crystal controlled and is used to generate a clock frequency. parity a technique for testing transmitted data. typically, a bi nary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked loop (pll) an electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts the pin number assignment: the relation between the logical inputs and outputs of the psoc device and their physical counterparts in the printed circuit board (pcb) package. pinouts involve pin numbers as a link between schematic and pcb design (both being computer generated files) and may also involve pin names. port a group of pins, usually eight. power-on reset (por) a circuit that forces the psoc device to reset when the volta ge is below a pre-set level. th is is one type of hardware reset. psoc ? cypress semiconductor?s psoc ? is a registered trademark and progra mmable system-on-chip? is a trademark of cypress. psoc designer? the software for cypress? programmable system-on-chip technology. pulse width modulator (pwm) an output in the form of duty cycle which varies as a function of the applied value. ram an acronym for random access memory. a data-storage device from which data can be read out and new data can be written in. register a storage device with a specific capacity, such as a bit or byte. reset a means of bringing a system back to a know n state. see hardware reset and software reset. rom an acronym for read only memory. a data-storage devi ce from which data can be read out, but new data cannot be written in. serial 1. pertaining to a process in which all events occur one after the other. 2. pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time the time it takes for an output signal or value to stabilize after the input has changed from one value to anothe r. glossary (continued)
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 48 of 50 shift register a memory storage dev ice that sequentially shifts a wo rd either left or right to ou tput a stream of serial data. slave device a device that allows another device to control the timing for data exchanges between two devices. or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external inte rface. the controlling device is called the master device. sram an acronym for static random access memory. a memory device where you can store and retrieve data at a high rate of speed. the term static is used because, after a value is loaded into an sram cell, it remains unchanged until it is explicitly altered or unt il power is removed from the device. srom an acronym for supervisory read only memory. the srom holds code that is used to boot the device, calibrate circuitry, and perform flash operations. the functions of the srom may be accessed in normal user code, operating from flash. stop bit a signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. a signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. a system whose operation is syn chronized by a clock signal. tri-state a function whose output can adopt three states: 0, 1, and z (hig h-impedance). the function does not drive any value in the z state and, in many respects, may be c onsidered to be disconnected from the rest of the circuit, allowing another output to drive the same net. uart a uart or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. user modules pre-built, pre-tested hardware/f irmware peripheral functions that take ca re of managing and configuring the lower level analog and digi tal psoc blocks. user module s also provide high level api (application programming interface) for the peripheral function. user space the bank 0 space of the register map. the registers in this bank are more likely to be modified during normal program execution and not just during initialization. register s in bank 1 are most likely to be modified only during the initialization phase of the program. v dd a name for a power net meaning "voltage drain". the most positive power supply signal. usually 5 v or 3.3 v. v ss a name for a power net meaning "voltage source." the most negative power supply signal. watchdog timer a timer that must be serviced periodically. if it is not serviced, the cpu resets after a specified period of tim e. glossary (continued)
cy8c24223a, cy8c24423a document number: 001-52469 rev. *h page 49 of 50 document history page document title: cy8c24223a, cy8c24423a automotive psoc ? programmable system-on-chip document number: 001-52469 revision ecn orig. of change submission date description of change ** 2678061 vivg/pyrs 03/24/09 new data sheet for automotive a-grade *a 2685606 shea 04/08/09 minor ecn to correct the spec number in document history. *b 2702925 btk 05/06/2009 post to external web *c 2742354 btk/pyrs 07/22/09 changed title. updated features sectio n. updated text of psoc functional overview section. updated getting start ed section. made corrections and minor text edits to pinouts section. change d the name of the register reference section to "registers". added clarifying comments to some electrical specifica- tions. updated some figures. changed t ramp specification per masj input. fixed all ac specifications to conf orm to a 5% imo accuracy. made other miscellaneous minor text edits. delet ed some non-applicable or redundant infor- mation. added a footnote to clarify that 8 of the 12 analog inputs are regular and the other 4 are direct sc block connections. updated development tool selection section. *d 2822792 btk/aesa 12/07/2009 added t prgh, t prgc, i ol , i oh , f 32ku , dc ilo , and t powerup electrical specifi- cations. corrected the flash ent electrical specificatio n. updated all footnotes for table 20, ?dc programm ing specifications,? on page 26. added maximum values and updated typical values for t eraseb and t write electrical specifica- tions. replaced t ramp electrical specification with sr powerup electrical speci- fication. added ?contents? on page 2. *e 2888007 njf 03/30/2010 updated cypress website links. removed reference to psoc designer 4.4. added t baketemp and t baketime parameters in absolute maximum ratings on page 14. updated 3.3 v dc analog reference specifications on page 21. removed third party tools and build a psoc emulator into your board. updated links in sales, solutions, and legal information . *f 3070556 btk 10/25/2010 added CY8C24223A-24PVXA(t) devices to datasheet. updated the following sections: getting started , development tools , and designing with psoc designer moved acronyms and document conventions to the end of document. added reference information and glossary sections. updated datasheet as per cypress styl e guide and new datasheet template. *g 3110316 btk/njf 05/12/11 updated i 2 c timing diagram to improve clarity. updated wording, formatting, and notes of the ac digital block specifications table to improve clarity. added v ddp , v ddlv , and v ddhv electrical specifications to give more information for programming the device. updated solder reflow temperature sp ecifications to give more clarity. updated the jitter specifications. updated psoc device characteristics table. updated the f 32ku electrical specification. updated note for r pd electrical specification. updated note for the t stg electrical specification to add more clarity. added tape and reel information section. added c l electrical specification. updated analog reference specifications. *h 3980449 aesa 04/24/13 updated figure 16 and figure 17 .
document number: 001-52469 rev. *h revised april 24, 2013 page 50 of 50 psoc designer? and programmable system-on-chip? are trademarks and psoc? and capsense? are registered trademarks of cypress sem iconductor corporation. purchase of i 2 c components from cypress or one of its sublicensed a ssociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. as from october 1st, 2006 philips semiconductors has a new trade name - nxp sem iconductors. all products and company names mentioned in this document may be the trademarks of their respective holders. cy8c24223a, cy8c24423a ? cypress semiconductor corporation, 2009-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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